Push-pull circuits are well known and have been adapted to digital and analog applications as varied as stepping motor control, audio loudspeakers, and memory systems. In the present context, push-pull circuits have been used in bus systems including one or more devices that output data onto a common bus. As used throughout, the term “bus” refers to one or more conductive paths communicating electrical signals between two points.
Push-pull circuits have excellent drive characteristics. That is, push-pull circuits routinely provide clean rising and falling edges for high speed data signals being driven onto a bus. This capability is realized by effective control of two stages generically illustrated in Figure (FIG.) 1.
In FIG. 1, a push-pull drive circuit is shown as implemented in CMOS and comprises a PMOS-transistor first stage 1 and NMOS-transistor second stage. In theory, the effective switching of the first and second stages controls a current path between a voltage source (Vss) and ground. Ideal switching by the input signal 3 of ideal first and second stages (i.e., perfectly sized and implemented CMOS devices) produces an ideal output signal 4, shown as curve “A” in the graph of FIG. 2. The production of this ideal output signal requires an exact actuation timing relationship between the first and second stages of the push-pull driver. This relationship requires that the switching input signals turn OFF one stage of the push-pull driver while simultaneously turning ON the other stage.
However, as one would expect, process variations in the fabrication of the first and second stage CMOS devices, as well as variations in device performance due to operating voltage and temperature variations, (collectively and generically referred to hereafter as “PVT” for process, voltage and temperature), result in very different output curves. For example, curve “B” shown in FIG. 2 illustrates an occurrence in which both stages of the push-pull driver are simultaneously OFF and a voltage knee momentarily forms in the output signal before one of the stages turns ON. Curve “C” in FIG. 2 illustrates an occurrence in which both stages of the push-pull driver are simultaneously ON and current momentarily “shoots-through” the channel between Vss and ground.
In a digital system, this shoot-through phenomenon is well understood and results in considerable noise being transmitted onto the bus, absent some design remedy. Historically the remedy has come in the form of a large by-pass capacitor shunting the shoot-through current to a ground plane in the CMOS substrate. Unfortunately, as bus systems are required to run at ever increasing data rates this brute force method of dealing with shoot-through becomes less and less acceptable. This is particularly true where bus widths are wide and where data signals are driven onto the bus using multiple clocks and/or multiple clock edges.
Many conventional double-data-rate (“DDR”) memory systems use push-pull drivers to communicate data between bus system devices and the bus. This approach differs from other bus systems having integrated circuit using simpler, open-drain output drivers. As DDR memory systems and similar data communication systems push the envelop for high-speed data transfer, push-pull shoot-through noise and the corresponding charge dump via by-pass capacitors becomes increasing unacceptable.
It is further understood that by placing a “pre-driver circuit” in front of a push-pull driver performance of the push-pull driver may be enhanced. Looking at the simplified circuit shown in FIG. 3 as an example, an adjustable pre-driver 20 precedes the push-pull driver 21. This combination is shown in greater detail in FIG. 4, wherein the push-pull driver is formed by the combination of P0 and N0 connected between a voltage source and ground.
Conventionally, selected control signals sampled from the pre-driver circuit are used to monitor (or sense) the integrity of the switching signal(s) applied to the push-pull driver. For example, by comparing the timing of a voltage waveform taken at point—A—in the PMOS driver 22 of FIG. 4 with the timing of a voltage waveform taken at point—A′—in the NMOS driver 23 of FIG. 4, one may roughly understand the quality of the switching signals. However, such pre-driver sensing techniques do not account for PVT affects at the PMOS and NMOS output transistors. Nor does pre-driver sensing detect or address the problem of shoot-through.